Fundamentals of digital circuit logic, including Boolean algebra; Karnaugh maps; multiplexers, decoders, ROMS, PLAS, flip-flops, counters; sequential networks; and state tables.
This course requires the Altera DE0-CV FPGA Lab Kit.
Please contact the department Lab Manager at least two weeks before the start of the semester to obtain the lab kit. Below is the contact information:
Textbooks and Materials
Please check the CSU Bookstore for textbook information. Textbook listings are available at the CSU Bookstore about 3 weeks prior to the start of the term.
Anura Jayasumana is a Professor in Electrical and Computer Engineering Department at CSU, where he also holds a joint appointment in the Department of Computer Science.
Dr. Jayasumana’s areas of expertise include Computer and Communication Networks, Distributed and Embedded System Design, and VLSI and PCB Testing. He has served as the Principal Investigator/Co-PI of several DARPA (Defense Advanced Research Projects Agency), NSF (National Science Foundation), and industry funded projects in these areas. He is currently a member of NSF Engineering Research Center for Collaborative Adaptive Sensing of the Atmosphere. He has supervised over 70 M.S. and 20 Ph.D. theses, and taught courses ranging from freshmen course on Logic Design, to graduate courses in Internet Engineering, Microprocessors, and VLSI Design Automation. He holds two patents, and is the co-author of over 200 peer reviewed papers. His recent professional activities include keynote speeches, seminars and short courses on sensor networking.